The present invention relates to a method of alignment between a mask pattern and a wafer pattern for a projection exposure system.
An alignment between a mask pattern and a wafer pattern is conducted for exposure of a mask pattern or a reticule to a resist applied on a wafer. As semiconductor integrated circuit patterns have been required to be scaled down, a highly accurate alignment between the mask pattern and the wafer pattern has also been required. In general, the accuracy of alignment between the mask pattern and the wafer pattern should be within one quarter or one third of the minimum design size. For example, 64-mega dynamic random access memory has a minimum design size of 0.35 micrometers. In this case, the accuracy of alignment between the mask pattern and the wafer pattern should be within 0.10 micrometers. 256-mega dynamic random access memory has a minimum design size of 0.25 micrometers. In this case, the accuracy of alignment between the mask pattern and the wafer pattern should be within 0.07 micrometers. 1-giga dynamic random access memory has a minimum design size of 0.18 micrometers. In this case, the accuracy of alignment between the mask pattern and the wafer pattern should be within 0.05 micrometers.
There are many factors which might influence to the alignment accuracy. In one viewpoint, those factors may be classified into two types. One is concerned with an alignment in chip and another is concerned with an alignment between chips or a shot array alignment.
FIG. 1 is a plan view illustrative of a conventional method of the shot array alignment. The shot array alignment is conducted as follows. Alignment marks are provided over a mask at a single point in each area corresponding to selected ones of the chips. Further, alignment marks ".times." 23 are also provided at top left corners of shot maps 22 over a wafer 21 so that the alignment marks ".times." 23 correspond in position to the alignment marks over the mask. The shot array alignment is conducted to align one of the mask alignment marks in each area to the corresponding one of the wafer alignment marks but there is not considered an issue of any further correspondences between the remaining mask alignment marks in the same area and the remaining wafer alignment marks.
FIG. 2 is a plan view illustrative of a conventional method of the chip-in-alignment. The chip-in-alignment is conducted as follows. Alignment marks are provided over a mask at plural points in each area corresponding to selected ones of the chips. Further, alignment marks ".times." 33 are also provided at four corners of shot maps 32 over a wafer 31 so that the alignment marks ".times." 33 correspond in position to the alignment marks over the mask. The chip-in-alignment is conducted to align the mask alignment marks to the corresponding ones of the wafer alignment marks.
The accuracy of the shot array alignment is likely to be influenced by an accuracy of an alignment sensor in an exposure system and an accuracy of a stage. In the meantime, the accuracy of chip-in-alignment is likely to be influenced by an expansion of the wafer in manufacturing processes, lens distortion and reticule or mask rotation.
Improvements in accuracy of the shot array alignment and the chip-in-alignment are important issues. If, however, the alignment is applied for manufacturing the 256-mega dynamic random access memory, then the accuracy of the chip-in-alignment is extremely important because if there exist errors in a constant magnification and a rotation in the chip, then the increase in size of the chip results in an increase in misalignment in the chip.
FIG. 3 is a schematic view illustrative of a conventional method of the alignment, wherein an exposure system is represented by a block diagram and broken lines represent traveling of light.
A semiconductor substrate 410 is fixed onto a wafer holder 411 by a vacuum suction force so that the semiconductor substrate 410 is mounted on a wafer stage 412. The wafer stage 412 is movable in X-directions, Y-directions and vertical directions under control of a control unit 404 so that a relative position between the semiconductor substrate 410 and a reticule 408 is adjusted.
The reticule 408 is first aligned to an exposure axis by use of a reticule alignment optical system which is not illustrated. Then, the semiconductor substrate 410 is aligned by use of an off-axis optical system 407 positioned outside the projection optical system, wherein the position is fixed with reference to the exposure axis. Namely, the wafer stage 412 is moved to a position under the off-axis optical system 407 so that an He--Ne laser 401 emits an alignment indent light 416 which is transmitted toward a reflection mirror 405. The alignment indent light 416 is hen reflected by the reflection mirror 405 and then transmitted through the off-axis optical system 407 onto an alignment mark not illustrated on the semiconductor substrate 410. The light 416 is diffracted by the alignment mark on the semiconductor substrate 410 and then a diffracted light 417 is transmitted toward a reflection mirror 406. The light 417 is then reflected by the reflection mirror 406 and then transmitted to a detector 403. The detector 403 detects the diffracted light 417 so as to detect a position of the alignment mark on the semiconductor substrate 410. The detector 403 outputs an alignment signal which is transmitted to an alignment signal processing unit 402 so that this information of the alignment mark position detected by the detector 403 is processed by the alignment signal processing unit 402. The processed signal is then sent to the control unit 404 so that the control unit 404 controls movements of the wafer stage 412 in accordance with the processes signal from the alignment signal processing unit 402. Namely the movement of the wafer stage 412 is controlled by the off-axis optical system 407 for realizing an indirect alignment before the wafer stage 412 mounted thereon with the semiconductor substrate 410 is moved to an exposure position thereby conducting an exposure of the pattern of the reticule 408 to the semiconductor substrate 410. It is also possible to use the optical system for exposure instead of the off-axis optical system so that an exposure light 415 is used as an alignment incident light to be transmitted through a projection lens 409. A wise-band wavelength light may be used as the alignment incident light for detection of the alignment mark position.
If at least one alignment mark is provided on each chip, then the shot array alignment selects plural chips so as to obtain positional information for individual alignment marks which are provided at the same positions of the individual chips. This method is disclosed by S. Slonaker et al, SPIE 922 (1988) 73p. This method will be described with reference again to FIG. 3. A single alignment mark is provided in each of the chips. On the basis of positional informations of the alignment marks of not less than ten chips over the semiconductor substrate 410, a shift, a scaling, a rotation and an orthogonality can be found. Those obtained parameters are used for feeding back to the movement of the wafer stage 412 holding the semiconductor substrate 410 in exposure process so that a highly accurate shot array alignment can be conducted.
If a plurality of the alignment marks are provided in each chip, then a chip scaling (magnification) and a chip rotation are found from the positional information of the alignment marks in the individual chips. In order to obtain those parameters both in X-direction and in Y-direction, it is necessary to measure positions of at least three alignment marks in each chip and if a highly accurate alignment is required, then at least four alignment marks are measured in those positions. It is of course preferable that the individual alignment marks are distributed in position within the chips. Those parameters are used for feeding back to the lens projection magnification, the rotation direction of the reticule 408 and the movements of the wafer stage 412 holding the semiconductor substrate 410 in the exposure process so that a highly accurate alignment may be conducted.
The above conventional alignment methods are, however, engaged with the following problems.
The shot array alignment is conducted based upon the positional information of a single alignment mark provided in the chip, for which reason from those available informations, no informations can be obtained about magnifications of the chip or the chip scaling and the chip rotation.
FIG. 4A is a plan view illustrative of a problem with chip scaling when alignment mark is normally provided at a corner of the rectangular-shaped chip. FIG. 4B is a plan view illustrative of a problem with chip rotation when the alignment mark is normally provided at a corner of the rectangular-shaped chip.
As illustrated in FIG. 4A, a single alignment mark ".largecircle." 53 is provided at a top left corner of a currently processing chip 51, whilst a single alignment mark ".largecircle." 54 is also provided at a top left corner of a previously processes chip 52. Even if there is a chip scaling between the currently processing chip 51 and the previously processed chip 52, then an alignment is conducted with reference to only the alignment marks ".largecircle." 53 and 54, for which reason it is impossible to confirm the presence of the chip scaling. If the alignment is made by superimposition of the alignment marks ".largecircle." 53 and 54, then an off-set in center of gravity is caused between the currently processing chip 51 and the previously processes chip 52, wherein the center of gravity is represented by ".times.".
As illustrated in FIG. 4B, even if there is a chip rotation between the currently processing chip 51 and the previously processes chip 52, then the alignment is conducted with reference to only the alignment marks ".largecircle." 53 and 54, for which reason it is impossible to confirm the presence of the chip rotation. If the alignment is made by superimposition of the alignment marks ".largecircle." 53 and 54, then an off-set in center of gravity is caused between the currently processing chip 51 and the previously processes chip 52, wherein the center of gravity is represented by ".times.".
In the meantime, the chip-in-alignment is conducted based upon positional information of a plurality of the alignment marks provided in each chip, for which reason the chip-in-alignment is free from the above problems with impossibility of confirmation of the presence of the chip scaling and chip rotation. However, it takes many times to refer to all of the alignment marks whereby it also takes many times to conduct the chip-in-alignment, resulting in a drop of the throughput. If, for example, the chip-in-alignment is conducted with reference to four alignment marks provided in each chip, the necessary time for conducting the chip-in-alignment is much longer by four times than when the shot array alignment is conducted with reference to only a single alignment mark provided in each chip. If the exposure is made to the 256-mega dynamic random access memory chips in 8-inches wafer, the throughput of the shot array alignment with reference to the single alignment mark provided in each chip is 55 wafers per hour, whilst the throughput of the chip-in-alignment with reference to the plural alignment marks provided in each chip is 26 wafers per hour.
In the above circumstances, it had been required to develop a novel method of a highly accurate alignment between mask pattern and wafer pattern while keeping a high throughput.